1. Field of the Invention
Generally, the present invention relates to the field of fabrication of integrated circuits, and, more particularly, to semiconductor devices having metal silicide portions on semiconductor regions to reduce the resistance of the semiconductor regions.
2. Description of the Related Art
In modern ultra-high density integrated circuits, device features are steadily decreasing to enhance device performance and functionality. Shrinking the feature sizes, however, entails certain problems that may partially offset the advantages obtained by the reduced feature sizes. Generally, reducing the feature sizes of, for example, a transistor element may lead to a decreased channel resistance in the transistor element and thus result in a higher drive current capability and enhanced switching speed of the transistor. In decreasing the features sizes of these transistor elements, however, the increasing electrical resistance of conductive lines and contact regions, i.e., of regions that connect transistor areas, such as drain and source regions, with the periphery of the transistor element, becomes a dominant issue, since the cross-sectional area of these lines and regions decreases with decreasing feature sizes. The cross-sectional area, however, determines, in combination with the characteristics of the material comprising the conductive lines and contact regions, the resistance thereof.
The above problems may be exemplified for a typical critical feature size in this respect, also referred to as a critical dimension (CD), such as the extension of the channel of a field effect transistor that forms below a gate electrode between a source region and a drain region of the transistor. Reducing this extension of the channel, commonly referred to as channel length, may significantly improve device performance with respect to fall and rise times, when operating the transistor element in a switched mode, due to the smaller capacitance between the gate electrode and the channel and due to the decreased resistance of the shorter channel. Shrinking of the channel length, however, also entails the reduction in size of any conductive lines, such as the gate electrode of the field effect transistor, which is commonly formed of polysilicon, and the contact regions that allow electrical contact to the drain and source regions of the transistor, so that consequently the available cross-section for charge carrier transportation is reduced. As a result, the conductive lines and contact regions exhibit a higher resistance unless the reduced cross-section is compensated for by improving the electrical characteristics of the material forming the lines and contact regions, such as the gate electrode, and the drain and source contact regions.
It is thus of particular importance to improve the characteristics of conductive regions that are substantially comprised of semiconductor material such as silicon. For instance, in modern integrated circuits, the individual semiconductor devices, such as field effect transistors, capacitors and the like, are primarily based on silicon, wherein the individual devices are connected by silicon lines and metal lines. While the resistivity of the metal lines may be improved by replacing the commonly used aluminum by, for example, copper and copper alloys, process engineers are confronted with a challenging task when an improvement in the electrical characteristics of silicon-containing semiconductor lines and semiconductor contact regions is required.
With reference to FIGS. 1a-1d, an exemplary process for manufacturing an integrated circuit containing, for example, a plurality of MOS transistors will now be described in order to illustrate the problems involved in improving the electrical characteristics of silicon-containing semiconductor regions in more detail.
In FIG. 1a, a semiconductor device 100, which may represent a MOS transistor, comprises a substrate 101, such as a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or any other appropriate carrier material on which is formed a silicon-containing semiconductor layer. For convenience, in FIG. 1a, the substrate 101 is to be considered as having formed thereon an appropriate silicon-containing layer, in which are formed drain and source regions 107 including appropriate extension regions 107e. As will be explained in the following, the drain and source regions 107 are to receive a metal silicide region therein so as to enhance the conductivity of the drain and source regions 107. Located between the drain and source regions 107 and the respective extension regions 107e is a channel region 102, above which is located a gate electrode 103, which may be comprised of polysilicon. The gate electrode 103 may also receive a metal silicide region thereon to reduce the resistivity. The gate electrode 103 is separated from the channel region 102 by an appropriate gate insulation layer 104, which may be comprised of, for instance, silicon dioxide, silicon nitride, or any other appropriate material composition. Moreover, spacer elements 106 including appropriate etch stop layers or liners 105 are formed at sidewalls of the gate electrode 103, wherein it should be appreciated that the spacers 106 and the etch stop layers 105 may represent two or more individual spacer elements and corresponding etch stop layers that may have been used during the formation of the semiconductor device 100 as shown in FIG. 1a. Finally, a protective layer 108 is formed above the substrate 101 to cover exposed portions of the semiconductor device 100, such as the gate electrode 103 including the spacers 106 and surface portions of the drain and source regions 107.
A typical process flow for forming the conventional semiconductor device 100 as shown in FIG. 1a may comprise the following processes. After the formation of appropriate active regions in the substrate 101, i.e., within a corresponding silicon-containing crystal-line layer, an appropriate vertical dopant profile may be established within the respective active regions by well-established isolation techniques, such as trench isolation techniques and the like, so as to allow the formation of transistor elements, capacitors and the like. For convenience, any such isolation structure and dopant profile is not shown in FIG. 1a. Thereafter, the gate insulation layer 104 may be formed by appropriate oxidation and/or deposition techniques, during which an insulating layer having a desired thickness and material composition is formed on the surface of the semiconductor device 100. As previously discussed, in modern integrated circuits, critical dimensions of circuit features, such as the gate length of MOS transistors, i.e., in FIG. 1a, the horizontal extension of the gate electrode 103, have reached 100 nm and significantly less. Hence, due to the reduced gate length, the cross-sectional area of the gate electrode 103 is also significantly reduced, thereby requiring an efficient technique for increasing the conductivity of the material in the gate electrode 103, which is typically accomplished by forming a metal silicide therein.
Thereafter, a gate electrode material, i.e., polysilicon, may be deposited by well-established low pressure chemical vapor deposition (LPCVD) followed by well-established photolithography techniques to pattern the gate electrode material, thereby forming the gate electrode 103 and the gate insulation layer 104, as shown in FIG. 1a. Next, the extension regions 107e and the drain and source regions 107 may be formed by a sequence of implantation processes, wherein the gate electrode 103 and any appropriate sidewall spacers may be used as an implantation mask. For instance, the spacers 106 may represent the entire spacer structure so as to obtain a laterally profiled dopant concentration as is required for the drain and source regions 107 and the extension regions 107e. Thereafter, or intermittently during the implantation sequence, appropriate anneal processes may be performed to activate the dopants and to substantially re-crystallize any crystalline defects caused by the preceding implantation. Next, the silicon dioxide layer 108 may be formed, for instance, by well-established chemical vapor deposition (CVD) techniques on the basis of TEOS or silane with a thickness of approximately 10-50 nm to appropriately protect the device 100 during the handling and processing for preparing the device 100 for the formation of metal silicide regions in the gate electrode 103 and the drain and source regions 107. That is, after the formation of the silicon dioxide layer 108, the device 100 may be conveyed to a corresponding silicidation module, in which further process steps for the formation of metal silicide regions may be performed.
Consequently, the semiconductor device 100 is subjected to a cleaning and removal process 109, wherein, in a first step, appropriate cleaning processes are performed to substantially remove any particles and metals from the silicon dioxide layer 108. Thereafter, the oxide layer 108 is removed by a wet chemical etch process on the basis of hydrofluoric acid (HF), wherein, in accordance with well-established process recipes, process parameters, such as temperature, concentration of the hydrofluoric acid, reaction time and the like, are adjusted to leave a significant portion of Si—H bonds on exposed silicon-containing surface portions, such as on the gate electrode 103 and the drain and source regions 107. Without intending to restrict the present application to the following explanation, it is believed that the Si—H surface is highly advantageous for the subsequent actual silicidation process to promote the chemical reaction between an appropriate metal to be deposited and the Si—H bonding containing surface portions.
FIG. 1b schematically shows the semiconductor device 100 after the cleaning and removal process 109, wherein the silicon dioxide layer 108 is removed. Moreover, the device 100 is subjected to a further cleaning and activation process 110, in which a sputter etch process is performed in an appropriate sputter deposition tool prior to the metal deposition process, thereby removing further contaminants from the exposed surface portions and also making the exposed silicon surface reactive with respect to the metal that is subsequently to be deposited. The corresponding surface portions activated by the particle bombardment in the sputter etch process 110 are indicated as 111. Thereafter, the process parameters of the process 110 are appropriately changed to initiate the deposition of an appropriate refractory metal, such as cobalt, nickel and the like, on the activated surface portions 111 and also on the insulating portions of the spacers 106.
FIG. 1c schematically shows the semiconductor device 100 with a correspondingly formed metal layer 112. After the deposition of the metal layer 112, the semiconductor device 100 may be subjected to a heat treatment to initiate diffusion of metal from the layer 112 into the activated portions 111, as is indicated by the corresponding arrows. Depending on the type of metal used, the temperature and the duration of the heat treatment may be selected so as to form a desired amount of metal silicide in the gate electrode 103 and the drain and source regions 107. For example, during the formation of a cobalt silicide, a first heat treatment may be performed at temperatures of approximately 500-600° C., thereby creating substantially cobalt monosilicide, which, however, typically exhibits a moderate high electrical resistance. After the first heat treatment, a second heat treatment at a lower temperature may be performed to convert a significant amount of cobalt monosilicide into a cobalt disilicide, which exhibits a desired low electric resistance. During the first and second heating steps or after the second heating step, an appropriately designed selective etch process may be performed to remove any non-reacted metal of the layer 112. It should be appreciated that other process schemes may be used, depending on the metal used and other process and device specific requirements. For instance, during the formation of a nickel silicide, the process parameters may be selected so as to substantially suppress the formation of nickel disilicide, since nickel disilicide exhibits a significantly higher electrical resistance compared to nickel monosilicide. Thereafter, appropriate heating steps may be performed to thermally stabilize the respective metal silicide formed in the gate electrode 103 and the drain and source regions 107.
FIG. 1d schematically shows the semiconductor device 100 after the completion of the above-described silicidation process so that corresponding metal silicide regions 114 are formed in the drain and source regions 107 and in the gate electrode 103. Although the metal silicide regions 114 may significantly enhance the conductivity of the respective regions, a number of difficulties may arise with the above-described conventional process sequence, in particular when extremely scaled semiconductor devices are considered, in which any non-uniformities of the metal silicide regions 114, as well as any defects, may considerably affect the overall behavior of the device 100. For example, silicide defects 114b may be observed on insulating areas, such as the sidewall spacers 106, which may be difficult to be removed and which may possibly provide a conductive path between actually isolated device regions. Moreover, regions 114a may be observed within the metal silicide regions 114, in which a reduced amount of metal silicide or no silicide at all has been formed during the preceding silicidation process, thereby rendering the corresponding metal silicide 114 highly non-uniform with respect to its current drive capability. Consequently, especially for highly scaled semiconductor devices, the area 114a may significantly degrade the overall performance of the semiconductor device 100.
In view of the situation described above, there exists a need for an improved technique that enables the formation of metal silicide regions while avoiding or at least reducing the effects of one or more of the problems identified above.